1. Technical Field
The present disclosure relates to a liquid crystal display device, and more particularly, to a gate driving unit for a narrow bezel and a liquid crystal display device including the gate driving unit.
2. Discussion of the Related Art
Recently, as the information society progresses, display devices processing and displaying a large amount of information have rapidly advanced and various flat panel displays (FPDs) have been developed. For example, the FPDs may include liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light emitting diode (OLED) display devices and field emission display (FED) devices.
In general, a display device includes a display panel displaying an image and a driving unit supplying a signal and a power to the display panel. The driving unit includes a gate driving unit and a data driving unit supplying a gate voltage and a data voltage, respectively, to a pixel region of the display panel, and a timing controlling unit controlling the gate driving unit and the data driving unit.
The gate driving unit includes a gate shift register generating a gate signal using a gate control signal.
FIG. 1 is a cross-sectional view showing a pull up transistor of an output buffering part in a gate shift register according to the related art, and FIG. 2 is a plan view showing a pull up transistor of FIG. 1.
In FIG. 1, a pull up transistor TU includes a gate electrode G, a gate insulating layer 13, an active layer 15, an ohmic contact layer 16, a source electrode S and a drain electrode D. The gate electrode G is formed on a substrate 11, and the gate insulating layer 13 is formed on the gate electrode G. The active layer 15 is formed on the gate insulating layer 13 over the gate electrode G, and the ohmic contact layer 16 is formed between the active layer 15 and the source electrode S and between the active layer 15 and the drain electrode D. The source electrode S and the drain electrode D are formed on the gate insulating layer 13 and are spaced apart from each other.
Although not shown, the gate electrode G of the pull up transistor TU is connected to a Q node, the drain electrode D of the pull up transistor TU is connected to a signal line supplying a clock signal, and the source electrode S of the pull up transistor TU is connected to a signal line outputting a gate signal.
Since the clock signal having a relatively high frequency and a relatively high voltage is applied to the drain electrode D of the pull up transistor TU, the gate signal outputted from the source electrode S of the pull up transistor TU may become unstable. To prevent the unstable gate signal, the pull up transistor TU may be formed to have a largest size among the transistors of the gate shift resistor.
In the pull up transistor TU, a first area a where the gate electrode G and the drain electrode D overlap each other is the same as a second area b where the gate electrode G and the source electrode S overlap each other (a=b). Since the first and second areas a and b are the same as each other, a capacitance of a parasitic capacitor between the drain electrode D and the gate electrode G is the same as a capacitance of a parasitic capacitor between the source electrode S and the gate electrode G.
In FIG. 2, the source electrode S and the drain electrode D overlap the gate electrode G. The source electrode S of the pull up transistor TU includes a plurality of first source electrodes S1 each having a bar shape and a second source electrode S2 connected to ends of the plurality of first source electrodes S1. The drain electrode D includes a plurality of first drain electrodes D1 each having a bar shape and a second drain electrode D2 connected to ends of the plurality of first drain electrodes D1. The second source electrode S2 and the second drain electrode D2 face into each other. The plurality of first source electrodes S1 and the plurality of first drain electrodes D1 are alternately disposed with each other and are spaced apart from each other. The other ends of the plurality of first source electrodes S1 are spaced apart from the second drain electrode D2, and the other ends of the plurality of first drain electrodes D1 are spaced apart from the second source electrode S2.
Each of the plurality of first drain electrodes D1 has the same width and the same length as each of the plurality of first source electrodes S1, and the plurality of first drain electrodes D1 and the plurality of first source electrodes S1 are spaced apart from each other by the same distance. As a result, the first area a where the drain electrode D and the gate electrode G overlap each other is the same as the second area b where the source electrode S and the gate electrode G overlap each other, and a plurality of channels are constituted between the plurality of first source electrodes S1 and the plurality of first drain electrodes D1.
A gate-in-panel (GIP) type LCD device where a gate driving unit is integrated in a display panel has been suggested, and the LCD device is required to have a narrow bezel which is defined as a width of a non-display region outside a display region for a slim design of a final product such as a monitor or a television as well as a light weight and a thin profile.
However, in the GIP type LCD device according to the related art, since the pull up transistor TU is formed to have a sufficient width W for the plurality of channels, it is limited to obtain the narrow bezel.